Why Do I See a “Unable to reset and halt CSoC” Error Message When I Attempt to Download to an E5 Device?

Why Do I See a “Unable to reset and halt CSoC” Error Message When I Attempt to Download to
an E5 Device?

This error message commonly occurs if you are using an external clock source—an external oscillator chip or crystal—to drive the E5 CSoC device and the external clock source is absent or malfunctioning.

After downloading a configuration image via JTAG, the CSoC device is reset. Immediately after reset, the E5 starts executing code using its internal ring oscillator as the clock source. As specified in your configuration image, it then switches over to your external clock source. If the external clock source is absent, it may appear that the E5 device is locked. FastChip Device Link (FDL) generates the following error message.

ERROR: download: Unable to reset and halt CSoC. Command halted.

You may not be able to download additional images. If downloading to RAM, you can easily clear this condition by cycling power to the board. If downloading to Flash, the image is already stored and power-cycling the board will not work.

Follow these steps to clear this condition.

Make sure that your external clock source is operating correctly. If using an external crystal, also see article #24548, “Why Doesn't the E5 Crystal Oscillator Amplifier Work?”

From within FastChip Device Link (FDL), click the Reset button in the toolbar, then CSoC Reset and Halt. This attempts to reset the CSoC device via JTAG. However, on the E5 device, the JTAG reset is synchronized to Bus Clock. Because Bus Clock is absent, i.e., Step 1 is not complete, this alone may not resolve the problem.

Click Reset from the FDL toolbar and select "CSoC Reset and Halt".

Press the reset button on the board. If the E5 target board does not have a reset button, momentarily ground the RST- pin via a resistor.

Press the Reset button or momentarily ground RST- to ground via a resistor.

If you were not able to verify that your external clock source is operating, make a new configuration image but using the Internal Ring Oscillator instead. Doing so allows you to debug the reset of your design without the external clock source. Click Save and Download to download your configuration image via JTAG.

Any UARTs or other logic that requires a precise time base will not work properly when using the internal ring oscillator as the clock source. The frequency of the internal ring oscillator varies with temperature, voltage, and between different devices.

FastChip Version: 2.3.0

This solution may or may not apply to other versions of the FastChip development system.